PIC18F8585T-I/PT【PDF 164/424 页】IC PIC MCU FLASH 24KX16 80TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3881

160页 161页 162页 163页 [164页]165页 166页 167页 168页

PIC18F6585/8585/6680/8680

DS30491C-page 244

2004 Microchip Technology Inc.

18.3

USART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit

SYNC (TXSTA<4>). In addition, enable bit, SPEN

(RCSTA<7>),

set

in order

configure

the

RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and

DT (data) lines, respectively.

The Master mode indicates that the processor trans-

mits the master clock on the CK line. Clock polarity is

selected with the SCKP bit (BAUDCON<5>); setting

SCKP sets the Idle state on CK as high, while clearing

the bit sets the Idle state as low. This option is provided

to support Microwire devices with this module.

18.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 18-2. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

Once the TXREG register transfers the data to the TSR

and interrupt bit TXIF (PIR1<4>) is set. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TXIE (PIE1<4>). Flag bit TXIF will be set regardless of

the state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register.

While flag bit TXIF indicates the status of the TXREG

tus of the TSR register. TRMT is a read-only bit which is

set when the TSR is empty. No interrupt logic is tied to

this bit so the user must poll this bit in order to determine

if the TSR register is empty. The TSR is not mapped in

data memory so it is not available to the user.

To set up a synchronous master transmission:

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-10:

SYNCHRONOUS TRANSMISSION

bit 0

bit 1

bit 7

Word 1

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2

bit 0

bit 1

bit 7

RC7/RX/DT

RC6/TX/CK

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit

‘1’

Word 2

TRMT bit

Write Word 1

Write Word 2

Note:

Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

RC6/TX/CK

(SCKP = 0)

(SCKP = 1)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式